1. Field of the Invention
The present invention relates to a time-division multiplexer which multiplexes/demultiplexes data and which includes relaying.
2. Description of the Related Art
FIG. 19 shows an example of a conventional multiplexer/demultiplexer located at a transmitting/receiving node.
In the figure, a timing pulse generator (PG) 1 generates and controls various kinds of timing pulses. A terminal interface 2 connects and controls the interface to terminals. Data from the terminal interface 2 are exchanged using a time-slot interchanger (TSI) 3 connected to a transmission interface 4. The transmission interface 4 is connected to and controls the interface to a transmission line. A multiplexing/demultiplexing bus 5 for received data multiplexes/demultiplexes received data from each interface to the TSI 3. A multiplexing/demultiplexing bus 6 for transmitting data multiplexes/demultiplexes transmitting data from the TSI to each interface. The timing pulses of nodes generated by the PG 1 are received and transmitted by a bus 7.
FIG. 20 shows an example of multiplexing/demultiplexing at a relay node according the conventional bit multiplexing system. The same reference numbers and legends are used for elements which are the same or similar to the elements shown in FIG. 19, for the sake of clarity. A transmission Interface 8 connects and controls the interface to a transmission line.
FIG. 21 shows signal timings at the relay node of the conventional bit multiplexing system. The reference numbers 401, 402, etc., refer to the signals shown in FIG. 20. The direction of writing/reading the data to/from the time-slot-conversion memories A, B in the TSI is reversed every multi-frame (every 20 frames).
FIG. 22 shows signal timings of receiving the data at the transmission interface of the conventional bit multiplexing system. The reference numbers 401, 402, etc., refer to the signals shown in FIGS. 19 and 20. The clock pulse rated of transmission line extract clock 405 differs from that of internal bus clock 406 of the node, so that the transmission speed of the data must be converted. Thus, asserted bits of signal 403 are transmitted from the transmission line.
FIG. 23 illustrates an example of a network of channels of the bit multiplexing system. In the figure, data is transmitted from/received at transmitting/receiving nodes N1, N2 and N4 and the data is relayed at a relay node N3. A transmission line (A) is between N1 and N3, a transmission line (B) is between N2 and N3, and a transmission line (C) is between N3 and N4. There are five terminals a, b, c, d and e at N1. The "terminals a and b" at N1 are connected to "terminals a' and b'" at N2 through N3, respectively. The "terminals c, d and e" at N1 are connected to "terminals c', d' and e'" at N4 through N3, respectively. Channels are defined as follows: from "terminal a" to "terminal a'", N1-N3 is defined as "channel a" and N3-N2 as "channel a'"; from "terminal b" to "terminal b'", N1-N3 as "channel b" and N3-N2 as "channel b'"; from "terminal c" to "terminal c'", N1-N3 as "channel c" and N3-N4 as "channel c'"; from "terminal d" to "terminal d'", N1-N3 as "channel d" and N3-N4 as "channel d'"; and from "terminal e" to "terminal e'", N1-N3 as "channel e" and N3-N4 as "channel e'". Data are transmitted at a different speed in each channel as follows: in channels a, a' at 8 kbps; in channels b, b' at 9.6 kbps; in channels c, c' at 4.8 kbps; in channels d, d' at 9.6 kbps; and in channels e, e' at 400 bps.
At the relay node, each channel is assigned to each of the transmission lines between two nodes. The data is exchanged at the relay node with a channel unit.
FIG. 24 shows a configuration of the time-slot-conversion memories A, B in the TSI, namely, the time-slot-conversion memories 32, 33 shown in FIGS. 19 and 20. In the figure, Z shows a number of bits included in one frame of the multiplexing/demultiplexing bus in the node.
In this configuration, the capacity of the time-slot-conversion memories becomes 2.times.20.times.Z=40Z (addresses) including the time-slot-conversion memories A and B.
In the following explanation, x and y of (x, y) show a bit number corresponding to the frame and a multi-frame number, respectively. (x, y) shows a specific address in the time-slot-conversion memory. In the same way, in FIGS. 25-29, (x, y) indicates a specific address in the time-slot-conversion memory, i.e., (1, 19) shows the first memory element of the nineteenth frame.
FIGS. 25-29 show examples of the operation of the TSI at the relay node of the conventional bit multiplexing system.
FIG. 25 shows a frame-assignment to "channel a" in the transmission line (A) and "channel a'" in the transmission line (B) (from "terminal a" at N1 to "terminal a'" at N2 through N3). The same assignment is given to the received/transmitting data in the time-slot-conversion memory in the TSI at N3.
In FIG. 25, 1' (p+m, 1) indicates data 1' is written in/read from an address (p+m, 1) in the time-slot-conversion memory. The direction of writing/reading the data to/from the time-slot-conversion memories A and B in the TSI is reversed every multi-frame.
In the same way. FIG. 26 shows a frame-assignment to "channel b" and "channel b'" shown in FIG. 23 and assignment in the time-slot-conversion memory. FIG. 27 shows a frame-assignment to "channel c" and "channel c'" shown in FIG. 23 and an assignment in the conversion memory. FIG. 28 shows a frame-assignment "channel d" and "channel d'" shown in FIG. 23 and an assignment in the conversion memory. FIG. 29 shows a frame-assignment to "channel d" and "channel d'" shown in FIG. 23 and an assignment in the conversion memory.
FIG. 30 illustrates an example of a network of paths and channels of another conventional multiplexing system, the so-called "bit-octet multiplexing system".
In the figure, N1, N2 and N4 show transmitting/receiving nodes and N3 shows a relay node. In tills system, a path is defined and used in each transmission line From the receiving node to the transmitting node according to transmission speed of data, 64 kbps.times.n. Channels are assigned respectively in each path. The data is switched with a path unit at N3. In the figure, a path "circle 1" is from N1 to N2 (N1-N3 -N2), in which a channel from "terminal a" at N1 to "terminal a'" at N3 and another channel from "terminal b" at N1 to "terminal b'" at N3 are assigned. In another path "circle 2" from N1 to N4 (N1-N3-N4), channels are assigned in the same way.
FIG. 31 shows an example of the operation of the TSI at the relay node of the conventional bit-octet multiplexing system. In the figure, the data is also switched in the TSI at N3 with a path unit.
In the following, demultiplexing and multiplexing data at the transmitting/receiving node will be explained.
The system for multiplexing data from the terminal to the transmission line will be explained first. FIG. 19 shows multiplexing/demultiplexing data at the transmitting/receiving node according to the conventional bit multiplexing system. Terminal data 201, which is received by a receiver 21 In the terminal interface 2, is written in a timing-conversion buffer memory 22 by a terminal clock pulse (204/205), which is received by a receiver 26. The data 201 is output to the multiplexing/demultiplexing bus 5 for received data as a signal 203 by a read-timing pulse 206 from the timing bus 7, and is written In the time-slot-conversion memory 32/33 as a signal 302/303 by a timing pulse 305/306/307 through a selector 31 in the TSI 3. The data is then transmitted to the multiplexing/demultiplexing bus 6 for transmitting data as a signal 304 by the timing pulse 305/306/307 through the selector 31, and is written in a timing-conversion buffer memory 47 as a signal 410 by a write-timing pulse 413 from the timing bus 7. The data is read as a signal 411 by a clock pulse 415 of a transmission line clock 46 and is output as a signal 412 to the transmission line by a driver 48.
Demultiplexing of data from the transmission line to the terminal will be explained below. Transmission line data 401, which is received by a receiver 41 in the transmission interface 4, is written in a timing-conversion buffer memory 43 as a signal 402 by a clock pulse 405, which is extracted by a transmission line clock extractor 42. The data is read by a read-timing pulse 406 from the timing bus 7. A multi-frame synchronization detector detects a multi-frame synchronizing bit, and the data is written in an MFA (multi-frame alignment memory) 45 as a signal 403 based on a multi-frame phase signal 407. The data is transmitted to the multiplexing/demultiplexing bus 5 for received data as a signal 404 by a read-timing pulse 408 from time timing bus 7. The data is thus written in the time-slot-conversion memory 32/33 as the signal 302/303 by the timing pulse 305/306/307 from the timing bus 7 through the selector 31 in the TSI 3.
The data is then output to the multiplexing/demultiplexing bus 6 for transmitting data as the signal 304 by the timing pulse 305/306/307 and is written in a timing-conversion buffer memory 24 of the terminal interface 2 as a signal 207 by a write-timing pulse 210 from the timing bus 7. The data is read and transmitted as a signal 208 by a clock pulse 212 of a terminal clock 23, and transmitted to the terminal as a signal 209 by a driver 2S. The terminal clock pulse is also output to the terminal by a driver 27.
A simultaneous timing generator 12 generates timing pulses 102, which were described above as various kinds of timing pulses. The PG 1 outputs the timing pulses 102 to the timing bus 7 through a bus driver 11 as signals 101.
A delay which occurs in multiplexing/demultiplexing will be explained with reference to the above figures and FIG. 22. In the configuration as shown in FIG. 19, the MFA 45 has to absorb a phase difference between multi-frame phase of the received data from the transmission line and internal multi-frame phase of the node (read timing from the timing bus 7), which causes a delay of one multi-frame (in this example, 2.5 msec (125 .mu.sec.times.20) at maximum because one multi-frame consists of 20 frames).
The time-slot-conversion memories 32 and 33 in the TSI 3 have to absorb a phase difference between the write timing from the timing bus 7 and read timing from the timing bus 7, which also causes a delay.
In the same way, In case of transmitting data to the transmission line, a delay occurs because the time-slot-conversion memories 32 and 33 in the TSI 3 have to absorb a phase difference between the write timing from the timing bus 7 and the read timing from the timing bus 7.
Multiplexing/demultiplexing the data at the relay node of the conventional bit multiplexing system is explained below with reference to FIG. 20. The operation of multiplexing/demultiplexing data at the relay node is similar to the operation at the transmitting/receiving node.
Transmission line data 801, which is received in the transmission interface 8, is written in a timing-conversion buffer memory 83 as a signal 802 and is read as a signal 803 by a read-timing pulse 806 from the timing bus 7. Multi-frame synchronizing bit is detected and the data is written in MFA (multi-frame alignment memory) 85 based on a multi-frame phase signal 807 of the received data. The data is output to the multiplexing/demultiplexing bus 5 for the received data as a signal 804 by a read-timing pulse 808 from the timing bus 7, and is written in the time-slot-conversion memory 32/33 in the TSI 3 as the signal 302/303 by the timing pulse 305/306/307.
The data is transmitted to the multiplexing/demultiplexing bus 6 for the transmitting data as the signal 304 by the timing pulse 305/306/307, and is written in the timing-conversion buffer memory 47 in the transmission interface 4 as the signal 410 by the write-timing pulse 413. This is read as the signal 411 by the clock pulse 415 and output to the transmission line as the signal 412. In case of relaying data from the transmission line (B) to the transmission line (A), the operation is the same as described above.
The simultaneous timing generator 12 generates the timing pulses 102, which were described above as various kinds of timing pulses. The PG 1 outputs the timing pulses 102 to the Liming bus 7 through the bus driver 11 as signals 101.
The MFA 85 has to absorb a phase difference between multi-frame phase of the received data from the transmission line (A) and internal multi-frame phase of the node (read timing from the timing bus 7), which causes a delay of one multi-frame (in this example, 2.5 msec (125 .mu.sec.times.20) at maximum because one multi-frame consists of 20 frames).
The time-slot-conversion memories 32 and 33 in the TSI 3 have to have capacity 2 multi-frame size for exchanging data with a multi-frame unit to/from the channel. This causes a delay of one multi-frame (in this example, 2.5 msec (125 .mu.sec.times.20) as shown by t3 in FIG. 21 because one multi-frame consists of 20 frames).
Another conventional "bit-octet multiplexing" system will be explained in the following. The operation at the transmitting/receiving node is the same as the operation of the conventional bit multiplexing system, and is not explained here. At the relay node, the operation is almost the same as the bit multiplexing system. In the bit-octet multiplexing system, however, data is not exchanged with a channel unit, but an octet unit (64 kbps). The delay caused by exchanging data becomes one frame (125 .mu.sec) at the time-slot-conversion memories 2 and 33 in the TSI 3.
In this system, the delay at the relay node becomes shorter than the bit multiplexing system, but multiplexing efficiency is less than the bit multiplexing system because the data is relayed with a path unit of octet (64 kbps) regardless of existence of signals.